As IOT has expanded into industrial applications, several challenges need to be addressed, including the need for more connected, secure and affordable devices that can handle 5G and Hybrid IOT networks. Additionally, one must ensure that these devices and their related services have trusted identities, and can be deployed and interacted securely without having to worry about the IOT development costs and complexity needed to unleash the full potential of IOT.
TRASNA SOC Platform has been developed to meet all of these requirements, while offering the lowest Bill Of Materials to the market to scale up the deployment of massive IOT.
FOR NB-IOT DEVICES
TURNKEY SOLUTION SOC FOR DEVICE MAKERS
The emergence of 5G has facilitated huge NBIOT opportunities in which networks can meet the communication needs of billions of connected objects and where the NBIOT is part of 5G specifications. TRASNA NBIOT SOC family has been designed with the following objective:
Build an all-in-one NBIOT SOC solution allowing the execution of multiple applications running in ultra low power mode for longer life battery (10-year support) while enabling edge computing and optimizing the die size for cost-efficiency.
TRASNA new SAFE012M is a very small SOC embedding advanced components such as RISC-V Application processor, NBIOT Radio , iSIM and GNSS, embedded Flash with required software and services to operate securely.
- RISC-V CPU core running at @266MHz (CORTEX M4 level)
- 1 Mbyte of NVM Memory with 100K Endurance capability
- 128 Kbyte of Executable & Data RAM
- Integrated 6-Channel DMA for Memory fast access
- Hardware 32-bit CRC
- 2 QSPI, 1 I2C / I3C, 1 UART / USART
- CPU Core @160MHz
- 884 Kbyte of NVM
- 256 Kbyte of Executable & Data RAM
- ISO7816 USIM reader interface.
- Up to 9 GPIOs
- Radio range from 450 to 2200 MHz
- Handling Software Defined Radio (SDR)
- Delivered with proven NBIOT R15 stack
EMBEDDED FLASH MEMORY SUB-SYSTEM
- 2 Mbyte of shared NVM for the 3 Sub- Systems
- 64-bit Read
- 4 Kbyte sectors
- 10 years Data Retention
- 100K NVM native endurance
- Endurance improvement through the Retention RAM(s) usage
TAILORED SECURE PROCESSOR SUB-SYSTEM
- RISC-V CPU core @200MHz (CORTEX M3 level)
- 140 Kbyte of NVM
- 156Kbyte of Executable & Data RAM.
- Encrypted storage of iSE NVM content & secure download from NVM to RAM.
- Cryptologic algorithms through several approaches (full Software computation, accelerated computations with specific instructions and co-processors, full hardware solution for symetrics algorithms and Hash)
- Proven iSIM stack already deployed for millions of devices
- GNSS Capabilities, GPS – L1, Beidou – B1, Galileo – E1, Assisted and standalone modes
- FOTA (Firmware-Over-The- Air) support
- PUF solution that eliminates the need of enrolement phase
- Ultra Low-Power modes (10 years lifetime on battery)
- Edge computing capability thanks to high computing power
FOR ANY KIND OF RF DEVICES
Since the SAFE012M is purely optimized for NBIOT, our next-generation SoC SAFE022M is aimed at addressing more RF interfaces as IOT requires different kinds of continuously evolving connectivity options.
Each of these options has a range of advantages and disadvantages and do not fit for any use case. It is necessary to evaluate the best IOT wireless technology solution for your particular use case and business scope.
TRASNA SAFE022M has been designed with the following objectives:
Provide a fully flexible 3-Core Secure SOC architecture, allowing device makers to have one platform for any type of RF by reusing the entire software and adding the analog RF companion chip.Very small footprint SOC including high-performing RISC-V application processor, an iSIM, GNSS and embedded Flash offering seamless connectivity through any kind of Radio (Analog) Companion Chip (LORA, BT, WIFI, NBIOT, CATM, LTE, ZIGBEE, DASH7 & other sub-GHz Radios, GNSS …).
With its wide range of RF capabilities, TRASNA SAFE022M can be used for many different applications with possible reuse of developments between applications. The Multi core processor SOC reuses the same family of IPs and a similar architecture than the NBIOT SOC (SAFE012M) chip : 2 General Purpose Processor subsystems, 1 Secure Enclave subsystem.
In addition to the GP1, the GP2 subsystem has specific DSP capabilities to handle Radio support (DSP Accelerators) and some specific interfaces to connect to RF front-end chips (JESD207) & external SIM (USIM).
Can connect to any kind of Radio (Analog) Companion Chip (LORA, BT, WIFI, NBIOT, CATM, LTE, ZIGBEE, DASH7 & other sub-GHz Radios, GNSS …).
Radio DSP treatment can be handled by the GP2 processor thanks to the Radio accelerators. Radio Protocol Stack can be also handled by the GP2 processor. GP1 is more “dedicated” to the main application. GP2 uses standard JESD207 interface + SPI for Radio Companion control. Can also be connected to monolithic Radio chip (including stack) through SPI.
EVALUATION BOARD & SOFTWARE DEVELOPMENT KIT (SDK)
TRASNA software development kits (SDKs) provide all the components needed to start embedded system development. A generic SDK development board with a lot of peripheral and a demo board with a limited set of peripheral but better form factor
The THALIB driver layer provides a complete set of ready-to-use APIs that simplify the user application implementation.
Device Drivers is a set of drivers used on our Evaluation Kit. All BSP (Board Support Package) for Trasna Evaluation Kit